Phase-change materials may switch, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electric resistance of an amorphous material is significantly greater than the electric resistance of a crystalline material, it is possible to determine the phase of the material by measuring the resistance thereof. This enables the storage of a binary piece of information, which depends on the state of the phase-change material.
FIG. 1, which corresponds to FIG. 13 of U.S. Pat. No. 7,422,926 (corresponding to European Patent Application EP 1729355), incorporated by reference, is a cross-section view of two neighboring PCM cells. Two conductive vias 2 and 4, bordered with a conductive barrier layer 5, cross a dielectric layer 6. Each of the two vias is in contact with the emitter 7 of a transistor, not shown. The structure is covered with a silicon nitride layer 8 and then with a dielectric layer 10. Two cavities 11 are dug into dielectric layer 10 and into silicon nitride layer 8 to reach the top of vias 2 and 4. The inside of cavities 11 is covered with a thin layer of resistive material 12. Cavities 11 are then filled with a thin dielectric layer 14 and with a filling dielectric 16. The structure is covered with a silicon nitride layer 18 and with a bonding layer 19. The silicon nitride layer 18 and bonding layer 19 are etched to expose a portion 21 of the upper ring of resistive material above each via 2 or 4 but to leave a limited portion 20 of the upper ring of resistive material covered. The structure is covered with a phase-change material 22. Thus, at the level of each via, only a limited portion 21 of the upper ring of resistive material is in contact with the layer of phase-change material 22, so that a phase change can occur in an area 23 close to this limited portion 21.
To program such PCM cells, a current is conducted between vias 2 and 4, which corresponds to the memory cell to be programmed, and an electrode attached to the upper surface of layer 22. This current heats resistive material 12 and, by contact, area 23 up to a temperature greater than the phase-change temperature of material 22. Material 22 of area 23 changes phase and the memory is thus programmed.
As described in above-mentioned U.S. Pat. No. 7,422,926, in the case where the cell density increases, it is no longer possible to form a cavity 11 above each of vias 2 and 4. U.S. Pat. No. 7,422,926 then provides forming a single cavity for two memory cells instead of one per memory cell.
Such a device is illustrated in FIG. 2, which corresponds to FIG. 29 of U.S. Pat. No. 7,422,926. A dielectric layer 6 is crossed by two vias 2 and 4. The structure is covered with a silicon nitride layer 8 and with a dielectric layer 10. A cavity is dug into dielectric layer 10 and silicon nitride layer 8. The cavity extends laterally from via 2 to via 4, at least partially exposing the upper end of vias 2 and 4. The inside of the cavity is covered with a layer of resistive material 12 and with a dielectric layer 14. The materials of resistive material 12 and dielectric layer 14 located on the bottom of the cavity are, for example, removed by etching. The resulting cavity is filled with dielectric 16. The structure is covered with a phase-change material 22.
Thus, each lateral edge of the single cavity is covered with a resistive material which extends vertically between the via on which it is placed and an area 23 of phase-change material layer 22.